Parallel Points

Well, I’m “featured engineer” on EEWeb today. I never expected to ever have my name featured on the same page as such luminaries as Bob Pease, Jeri Ellsworth, Howard Johnson or Limor Fried, to name but 4 of the “engineering household names” on that list!

Xilinx and Altera have both announced FPGAs with hard ARM processors on them. Xilinx have even got a new product famliy name (Zynq) for them.

For want of a better place to log how to get at the dishwasher pump next time it gets stuck with a tiny piece of plastic blocking the impeller, I’m sticking it here.

In case it helps anyone else it’s a Bosch Classixx (no idea what model no, bought about 2004 IIRC)

• Turn it on its side (right hand side looking at the door - the one nearest the programme dial)
• remove the bottom (remove two screws and need a flat screwdriver to prise it a bit) - it has an earth wire attached, so don’t yank it completely away
• Don’t lose the bit of polystyrene from the anti-flooding switch!

I recently became aware of the EEWeb electronic design site (as one of their reps emailed me to see if I’d like my site to appear on their front page… we’ll see if my server can handle that soon!)

It’s sponsored by Digikey, much like RS’s DesignSpark and Farnell’s element14.

There’s an awful lot of content and I’ve barely scratched through a tiny bit of it - worth a trawl!

Some of my “useful bits” of library code have lived in libv.vhd for a while - I’ve split it off and licensed it with a CC0 license (which means the author disclaims copyright and offers no warranty). It’s on github and I’ll add contributions from anyone who has any!

Either individual functions to add to libv.vhd or great big wodges of useful code (like Jim Lewis’ randomized testing libraries maybe….)

I’m contributing to the VASG group which is working on coming up with what the next revision of VHDL should be able to do.

On today’s conference call, the idea was mooted that VHDL could allow the use of Unicode identifiers (ie entity, signal, variable names etc.).

All of today’s participants were (as far as I recall) native English speakers without much call for accented characters, much less characters from entirely different writing systems. So I’m putting a call out to see if there’s any interest from the wider community in pushing forwards a requirement for VHDL compilers to support Unicode.

Feel free to mail me, comment below or @mention me in a tweet with your thoughts - I’ll summarise the results here in a few weeks

@boldport asked:

What are your #FPGA design space exploration techniques?

which he expands upon:

“Design space exploration” is the process of trying out different settings and design methods for achieving better performance. Sometimes the goals are met without any of it – the default settings of the tools are sufficient. When they’re not, what are your techniques to meet your performance goals?

Yet again, the 140 character constraint leaves me with things unspoken….

@boldport recently asked on Twitter what version control software people used on their FPGA designs. I replied that I use git at home and Subversion at work. The reasons why take a bit more than 140 characters, so I’ve written them here!

A few weeks ago I read a blog post by the illustrious MS researcher Prof. Satnam Singh. He writes about his Kiwi project which he describes as “[trying] to civilise hardware design” - as compared to the explicit writing of state machines.

His example is a Ethernet processor which simply swaps the source and destination MAC addresses over and retransmits them. He has code in C#, and it looks a lot like the inferred state machine style of VHDL I’ve been toying with for a while.

So (finally) I’ve toyed…

And so, finally, after all that setup, some code to read PGM files and how to make use of it. Next stage will be writing some files!

As always, the code can be found on github